NXP Semiconductors MPC5566 - Reset Effects on SRAM Accesses

SRAM
MPC5566 Microcontroller Reference Manual, Rev. 2
14-4 Freescale Semiconductor
14.6.2 Reset Effects on SRAM Accesses
If a reset event asserts during a read or write operation to SRAM, the completion of that access depends
on the cycle at which the reset occurs. Data read from or written to SRAM before the reset event occurred
is retained, and no other address locations are accessed or changed.
NOTE
Standby memory can contain the previous data values if a reset occurs while
cache is running in copy back mode.
14.7 Initialization and Application Information
To use the SRAM, the ECC must check all bits that require initialization after power on. Use a 64-bit
cache-inhibited write to each SRAM location in the application initialization code to initialize the SRAM
array. All writes must specify an even number of registers performed on 64-bit word-aligned boundaries.
If the write is not the entire 64-bits (8-, 16-, or 32-bits), a read / modify / write operation is generated that
checks the ECC value upon the read. Refer to Section 14.6, “SRAM ECC Mechanism.”
NOTE
You must initialize SRAM, even if the application does not use ECC
reporting.
Write Operation
8-, 16-, or 32-bit write
Idle
1
Read
Pipelined 8-, 16-, or 32-bit write
2
64-bit write
8-, 16-, or 32-bit write 0
(write to the same address)
Pipelined 8-, 16-, or 32-bit write 8-, 16-, or 32-bit write 0
64-bit write
Idle
064-bit write
Read
64-bit burst write
Idle
0,0,0,064-bit write
Read
Table 14-3. Number of Wait States Required for SRAM Operations (continued)
Current Operation Previous Operation Number of Wait States Required