Deserial Serial Peripheral Interface (DSPI)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 20-11
20.3.2.2 DSPI Transfer Count Register (DSPIx_TCR)
The DSPIx_TCR contains a counter that indicates the number of SPI transfers made. The transfer counter
is intended to assist in queue management. The user must not write to the DSPIx_TCR while the DSPI is
running.
20
CLR_TXF
Clear TX FIFO. Flushes the TX FIFO. Write a 1 to the CLR_TXF bit to clear the TX FIFO counter. The
CLR_TXF bit is always read as zero.
0 Do not clear the TX FIFO counter
1 Clear the TX FIFO counter
21
CLR_RXF
Clear RX FIFO. Flushes the RX FIFO. Write a 1 to the CLR_RXF bit to clear the RX counter. The CLR_RXF
bit is always read as zero.
0 Do not clear the RX FIFO counter
1 Clear the RX FIFO counter
22–23
SMPL_
PT
[0:1]
Sample point. Allows the host software to select when the DSPI master samples SIN in modified transfer
format. Figure 20-36 shows where the master can sample the SIN pin. The following table lists the delayed
sample points.
24–30 Reserved
31
HALT
Halt. Provides a mechanism for software to start and stop DSPI transfers.
See Section 20.4.2, “Start and Stop of DSPI Transfers,” for details on the operation of this bit.
0 Start transfers
1 Stop transfers
Table 20-3. DSPIx_MCR Field Descriptions (continued)
Field Description
SMPL_PT
Number of system clock cycles between
odd-numbered edge of SCK[x] and sampling of SIN[x].
00 0
01 1
10 2
11 Invalid value
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