Enhanced Queued Analog-to-Digital Converter (eQADC)
MPC5566 Microcontroller Reference Manual, Rev. 2
19-98 Freescale Semiconductor
Figure 19-53. Example of External Multiplexing
19.4.7 eQADC eDMA/Interrupt Request
Table 19-54 lists methods to generate interrupt requests in the eQADC queuing control and triggering
control. The eDMA/interrupt request select bits and the eDMA/interrupt enable bits are described in
Section 19.3.2.7, “eQADC Interrupt and eDMA Control Registers 0–5 (EQADC_IDCRn),” and the
interrupt flag bits are described in Section 19.3.2.8, “eQADC FIFO and Interrupt Status Registers 0–5
(EQADC_FISRn).” Table 19-54 depicts all interrupts and eDMA requests generated by the eQADC.
AN71
AN70
AN69
AN68
AN67
AN66
AN65
AN64
MUX
40:1
ADC0
MUX
40:1
ADC1
MUX
Control
Logic
MUX
ANW
ANX
ANY
ANZ
Channel
Number 0/1
MA2
MA1
MA0
eQADC
4
40
36
AN79
AN78
AN77
AN76
AN75
AN74
AN73
AN72
MUX
AN87
AN86
AN85
AN84
AN83
AN82
AN81
AN80
MUX
AN95
AN94
AN93
AN92
AN91
AN90
AN89
AN88
MUX
AN16–AN39
AN0–AN7
AN12
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