NXP Semiconductors MPC5566 - Overrun Request Enable Register (SIU_ORER)

System Integration Unit (SIU)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 6-19
6.3.1.8 Overrun Request Enable Register (SIU_ORER)
The SIU_ORER contains bits to enable an overrun if the corresponding flag bit is set in the SIU_OSR. If
the overrun request enable bit and the flag bit are set, the single combined overrun request from the SIU
to the interrupt controller is asserted.
The following table describes the fields in the overrun request enable register:
Address: Base + 0x0024 Access: R/W
0 1 2 3 4 5 6789101112131415
R0 0 0 0 0 0 0000000000
W
Reset0 0 0 0 0 0 0000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
ORE
15
ORE
14
ORE
13
ORE
12
ORE
11
ORE
10
ORE
9
ORE
8
ORE
7
ORE
6
ORE
5
ORE
4
ORE
3
ORE
2
ORE
1
ORE
0
W
Reset0 0 0 0 0 0 0000000000
Figure 6-9. Overrun Request Enable Register (SIU_ORER)
Table 6-15. SIU_ORER Field Descriptions
Field Function
0–15 Reserved
16–31
OREn
Overrun request enable n. Enables the overrun request when an overrun occurs on the IRQ[n] pin. Bit 31 (ORE0) is
the enable overrun flag for IRQ[0]; bit 16 (ORE15) is overrun flag for IRQ[15].
0 Overrun request is disabled.
1 Overrun request is enabled.