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NXP Semiconductors MPC5566 - Chapter 22; Overview

NXP Semiconductors MPC5566
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Enhanced Modular Input/Output Subsystem (eMIOS)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 17-3
17.1.1 Overview
The eMIOS builds on the MIOS concept by using a unified channel module that provides a superset of the
functionality of all the individual MIOS channels, while providing a consistent user interface. This allows
more flexibility as each unified channel can be programmed for different functions.
17.1.2 Features
• 24 unified channels
• Unified channels features
— 24-bit registers for captured/match values
— 24-bit internal counter
— Internal prescaler
— Dedicated output pin for buffer direction control
— Selectable time base
— Can generate its own time base
• Four 24-bit wide counter buses
— Counter bus A can be driven by unified channel 23 or by the STAC bus.
— Counter bus B, C, and D are driven by unified channels 0, 8, and 16, respectively.
— Counter bus A can be shared among all unified channels. UCs 0 to 7 can share counter bus A
and B, UCs 8 to 15 can share counter bus A and C, and UCs 16 to 23 can share counter buses
A and D.
• One global prescaler
• Shared time bases through the counter buses
• Synchronization among internal and external time bases
• Shadow FLAG register
• State of module can be frozen for debug purposes
• DMA request capability for some channels
• Motor control capability

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