Enhanced Time Processing Unit (eTPU)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 18-31
18.4.4.3 eTPU Time Base 2 (TCR2) Visibility Register (ETPU_TB2R)
This register provides visibility of the TCR2 time base for core host read access. This register is read-only.
The value of the TCR2 time base shown can be driven by the TCR2 counter, the angle mode logic, or
imported from the STAC interface, depending on angle mode (an engine cannot import when in angle
mode) and STAC interface configurations set in registers ETPU_TBCR and ETPU_REDCR. For more
information on time bases, refer to the eTPU Reference Manual.
Address: Base + 0x0000_0028 (eTPU A)
Address: Base + 0x0000_0048 (eTPU B)
Access: R/O
0123456789101112131415
R00000000 TCR2
W
Reset0000000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R TCR2
W
Reset0000000000000000
Figure 18-12. eTPU Time Base 2 (TCR2) Visibility Register (ETPU_TB2R)
Table 18-13. ETPU_TB2R Bit Field Descriptions
Field Description
0–7 Reserved
8–31
TCR2
[0:23]
TCR2 value. Used on matches and captures. For information on TCR2, refer to the eTPU Reference Manual.
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