NXP Semiconductors MPC5566 - L1 Cache Configuration Register 0 (L1 CFG0)

e200z6 Core Complex
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 3-29
3.3.2.6 L1 Cache Configuration Register 0 (L1CFG0)
The L1 cache configuration register 0 (L1CFG0) is a 32-bit read-only register. L1CFG0 provides
information about the configuration of the Z650n3 L1 cache design. The contents of the L1CFG0 register
can be read using a mfspr instruction. The SPR number for L1CFG0 is 515 in decimal. The L1CFG0
register is shown in Figure 3-17.
The L1CFG0 bits are described in Table 3-10.
31 CE
Cache Enable
0 = Cache is disabled
1 = Cache is enabled
When disabled, cache lookups are not performed for normal load or store accesses.
Other L1CSR0 cache control operations are still available. Also, operation of the
store buffer is not affected by CE.
012345678910111213141516171819202122232425262728293031
CARCH
CWPA
CFAHA
CFISWA
0
CBSIZE
CREPL
CLA
CPA
CNWAY
CSIZE
01 10100 00 10 11
00000111 (8 way) /
00000011 (4 way)
00000100000 (32 KB)
SPR - 515; Read-only
Figure 3-17. L1 Cache Configuration Register 0 (L1CFG0)
Table 3-10. L1CFG0 Field Descriptions
Bits Name Description
0–1 CARCH
Cache architecture
01 - The cache architecture is unified
2CWPA
Cache way partitioning available
1 - The cache supports partitioning of way availability for I/D accesses
3CFAHA
Cache flush all by hardware available
0 - The cache does not support flush all in hardware
4CFISWA
Cache flush/invalidate by set and way available
1 - The cache supports flushing/invalidation by set and way via the L1FINV0 spr
5–6 — Reserved—read as zeros
7–8 CBSIZE
Cache block size
00 - The cache implements a block size of 32 bytes
9–10 CREPL
Cache replacement policy
10 - The cache implements a pseudo-round-robin replacement policy
11 CLA
Cache locking APU available
1 - The cache implements the line locking APU
Table 3-9. L1CSR0 Field Descriptions (continued)
Bits Name Description