NXP Semiconductors MPC5566 - Flexcan2 Addressing and RAM Size

MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 22-35
3. Initialize CANx_MCR bits MBFEN, SRXDIS, and WRNEN.
The initialization of FlexCAN registers for either global or individual acceptance masking depends
on the configuration of MBFEN:
— If MBFEN is negated, initialize CANx_RXGMASK, CANx_RX14MASK, and
CANx_RX15MASK registers for acceptance mask.
— If MBFEN is asserted, initialize CANx_RXIMR[0-63] for individual acceptance masking.
4. Set required mask bits in CANx_IMRH and CANx_IMRL registers (for all MBs interrupts), and
in CANx_CR (for bus off and error interrupts).
5. Negate the CANx_MCR[HALT] bit.
Starting with this last event, FlexCAN2 attempts to synchronize with the CAN bus.
22.5.2 FlexCAN2 Addressing and RAM Size
There are 1024 bytes of RAM for a maximum of 64 message buffers. You can program the maximum
number of message buffers (MBs) using the MAXMB field in the CANx_MCR. For a 1024-byte RAM
configuration, MAXMB can be any number from 0–63.