NXP Semiconductors MPC5566 - External Bus Operations

External Bus Interface (EBI)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 12-27
cases where two or more external transfers are required for one internal transfer request, the external
accesses are a small access set, as described in Section 12.4.2.6, “Small Accesses (Small Port Size and
Short Burst Length).”
Because all transfers are aligned on the external bus, normal timing diagrams and protocol apply. Do not
use the TSIZ[0:1] signals for misaligned accesses.
12.4.2 External Bus Operations
The following sections provide a functional description of the external bus, the bus cycles provided for
data transfer operations, bus arbitration, and error conditions.
Table 12-15. Misalignment Cases Supported by a 32-bit EBI (external bus)
Case
Number
1
1
Misaligned case numbers, from Table 12-14.
Program Size
and Byte Offset
Port Size ADDR[30:31]
2, 3
2
External ADDR pins are not necessarily the address on the internal master AHB bus.
3
Addresses designated by a ‘z’ use bit 29 to increment the transmit address to the next word.
For all other cases, address bit 29 is unchanged.
WE
[0:3]
4
4
External WE pins. These pins have negative polarity, opposite of the internal byte strobes in
Table 12-14.
1 Halfword @ 0x0001
0 = 32 bits 00 1001
1 = 16 bits
00
10
1011
0111
4
Halfword @ 0x0003
Two AHB transfers
0 = 32 bits
11
5
z00
5
Treated as 1-byte access.
1110
0111
1 = 16 bits 11
5
z00
1011
0111
8
Word @ 0x0001
Two AHB transfers
0 = 32 bits
00
z00
1000
0111
1 = 16 bits
00
10
1011
0011
9
Word @ 0x0002
Two AHB transfers
0 = 32 bits
00
z00
1100
0011
1 = 16 bits
10
z00
0011
0011
10
Word @ 0x0003
Two AHB transfers
0 = 32 bits 11
5
1110
1 = 16 bits 11
5
1011
11
Word @ 0x0003
Two AHB transfers
0 = 32 bits z00 0001
1 = 16 bits
z00
z10
0011
0111