NXP Semiconductors MPC5566 - Test Data Input (TDI)

Nexus
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 25-7
25.2.1.9 Test Data Input (TDI)
The TDI pin receives serial test instruction and data. TDI is sampled on the rising edge of TCK.
25.2.1.10 Test Mode Select (TMS)
The TMS pin is used to sequence the IEEE® 1149.1-2001 TAP controller state machine. TMS is sampled
on the rising edge of TCK.
25.3 Memory Map
The NDI block contains no memory mapped registers. Nexus registers are accessed by the development
tool via the JTAG port using a register index and a client select value. The client select is controlled by
loading the correct access instruction into the JTAG controller; refer to Table 25-4. OnCE registers are
accessed by loading the appropriate value in the RS[0:6] field of the OnCE command register (OCMD)
via the JTAG port.
Table 25-2 shows the NDI registers by Client Source ID and Index values.
Table 25-2. Nexus Development Interface (NDI) Registers
Client
Source ID
Index Register
e200z6 Control and Status Registers
1
0b0000 2 e200z6 Development Control1 (NZ6C3_DC1)
0b0000 3 e200z6 Development Control2 (NZ6C3_DC2)
0b0000 4 e200z6 Development Status (NZ6C3_DS)
0b0000 6 e200z6 User Base Address (NZ6C3_UBA)
0b0000 7 Read/Write Access Control/Status (NZ6C3_RWCS)
0b0000 9 Read/Write Access Address (NZ6C3_RWA)
0b0000 10 Read/Write Access Data (NZ6C3_RWD)
0b0000 11 e200z6 Watchpoint Trigger (NZ6C3_WT)
0b0000 13 e200z6 Data Trace Control (NZ6C3_DTC)
0b0000 14 e200z6 Data Trace Start Address 0 (NZ6C3_DTSA1)
0b0000 15 e200z6 Data Trace Start Address 1 (NZ6C3_DTSA2)
0b0000 18 e200z6 Data Trace End Address 0 (NZ6C3_DTEA1)
0b0000 19 e200z6 Data Trace End Address 1 (NZ6C3_DTEA2)
eDMA 1 Control and Status Registers
0b0001 2 eDMA 1 Development Control (NXDM_DC)
0b0001 11 eDMA 1 Watchpoint Trigger (NXDM_WT)
0b0001 13 eDMA 1 Data Trace Control (NXDM_DTC)