NXP Semiconductors MPC5566 - Pad Configuration Registers 44 (SIU_PCR44)

System Integration Unit (SIU)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 6-29
6.3.1.20 Pad Configuration Registers 44 (SIU_PCR44)
The SIU_PCR44 register controls the function, direction, and electrical attributes of
DATA[16]_FEC_TX_CLK_GPIO[44].
Figure 6-21. DATA[16]_FEC_TX_CLK_GPIO[44] Pad Configuration Registers (SIU_PCR44)
6.3.1.21 Pad Configuration Registers 45 (SIU_PCR45)
The SIU_PCR45 register controls the function, direction, and electrical attributes of
DATA[17]_FEC_CRS_GPIO[45].
Figure 6-22. DATA[17]_FEC_CRS_GPIO[45] Pad Configuration Registers (SIU_PCR45)
6.3.1.22 Pad Configuration Registers 46 (SIU_PCR46)
The SIU_PCR46 register controls the function, direction, and electrical attributes of
DATA[18]_FEC_TX_ER_GPIO[46].
Address: Base + 0x0098 Access: R/W
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0
PA OBE
1
1
When configured as DATA[16] or FEC_TX_CLK, the OBE bit has no effect. When configured as GPDO, set the OBE bit to 1.
IBE
2
2
When configured as DATA[16] or FEC_TX_CLK, set the IBE bit to 1 to show the pin state in the GPDI register.
Clear the IBE bit to 0 to reduce power consumption. When configured as GPDI, set the IBE bit to 1.
DSC ODE
3
3
When configured as DATA[16], clear the ODE bit to 0.
HYS
4
4
If external master operation is enabled, clear the HYS bit to 0.
0 0
WPE
5
5
Refer to the EBI section for weak pullup settings when configured as DATA[16].
WPS
5
W
RESET: 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1
Address: Base + 0x009A Access: R/W
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0
PA OBE
1
1
When configured as DATA[17] or FEC_CRS, the OBE bit has no effect. When configured as GPDO, set the OBE bit to 1.
IBE
2
2
When configured as DATA[17] or FEC_CRS, set the IBE bit to 1 to show the pin state in the GPDI register. Clear the IBE bit to
0 to reduce power consumption. When configured as GPDI, set the IBE bit to 1.
DSC ODE
3
3
When configured as DATA[17], clear the ODE bit to 0.
HYS
4
4
If external master operation is enabled, clear the HYS bit to 0.
0 0
WPE
5
5
Refer to the EBI section for weak pullup settings when configured as DATA[17].
WPS
5
W
RESET: 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1