NXP Semiconductors MPC5566 - DSPI PUSH TX FIFO Register (Dspix_Pushr)

Deserial Serial Peripheral Interface (DSPI)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 20-23
20.3.2.6 DSPI PUSH TX FIFO Register (DSPIx_PUSHR)
The DSPIx_PUSHR provides a means to write to the TX FIFO. Data written to this register is transferred
to the TX FIFO. See Section 20.4.3.4, “Using the TX FIFO Buffering Mechanism,” for more information.
Write accesses of 8- or 16-bits to the DSPIx_PUSHR transfers 32 bits to the TX FIFO.
NOTE
TXDATA is used in master and slave modes.
15
RFDF_DIRS
Receive FIFO drain DMA or interrupt request select. Selects between generating a DMA request or an
interrupt request. When the RFDF flag bit in the DSPIx_SR is set, and the RFDF_RE bit in the DSPIx_RSER
is set, the RFDF_DIRS bit selects between generating an interrupt request or a DMA request.
0 Interrupt request is selected
1 DMA request is selected
16–31 Reserved
Address: Base + 0x0034 Access: R/W
0123456789101112131415
R
CONT CTAS EOQ
CT
CNT
00
0 0 PCS5 PCS4 PCS3 PCS2 PCS1 PCS0
W
Reset0000000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
TXDATA
W
Reset0000000000000000
Figure 20-8. DSPI PUSH TX FIFO Register (DSPIx_PUSHR)
Table 20-7. DSPIx_RSER Field Descriptions (continued)
Field Description