Deserial Serial Peripheral Interface (DSPI)
MPC5566 Microcontroller Reference Manual, Rev. 2
20-24 Freescale Semiconductor
The following table describes the fields in the DSPI push transmit FIFO register:
Table 20-8. DSPIx_PUSHR Field Descriptions
Field Description
0
CONT
Continuous peripheral chip select enable. Selects a continuous selection format. The bit is used in SPI master mode.
The bit enables the selected PCS signals to remain asserted between transfers. See Section 20.4.7.5, “Continuous
Selection Format,” for more information.
0 Return peripheral chip select signals to their inactive state between transfers
1 Keep peripheral chip select signals asserted between transfers
1–3
CTAS
[0:2]
Clock and transfer attributes select. Selects which of the DSPIx_CTARs is used to set the transfer attributes for the
SPI frame. In SPI slave mode, DSPIx_CTAR0 is used. The following table shows how the CTAS values map to the
DSPIx_CTARs. There are eight DSPIx_CTARs in the device DSPI implementation.
Note: Use in SPI master mode only.
4
EOQ
End of queue. Provides a means for host software to signal to the DSPI that the current SPI transfer is the last in a
queue. At the end of the transfer the EOQF bit in the DSPIx_SR is set.
0 The SPI data is not the last data to transfer
1 The SPI data is the last data to transfer
Note: Use in SPI master mode only.
5
CTCNT
Clear SPI_TCNT. Provides a means for host software to clear the SPI transfer counter. The CTCNT bit clears the
SPI_TCNT field in the DSPIx_TCR. The SPI_TCNT field is cleared before transmission of the current SPI frame
begins.
0 Do not clear SPI_TCNT field in the DSPIx_TCR
1 Clear SPI_TCNT field in the DSPIx_TCR
Note: Use in SPI master mode only.
6–7 Reserved
8–9 Reserved, but implemented. These bits are writable, but have no effect.
CTAS
Use Clock and Transfer
Attributes from
000 DSPIx_CTAR0
001 DSPIx_CTAR1
010 DSPIx_CTAR2
011 DSPIx_CTAR3
100 DSPIx_CTAR4
101 DSPIx_CTAR5
110 DSPIx_CTAR6
111 DSPIx_CTAR7
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