Enhanced Serial Communication Interface (eSCI)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 21-9
NOTES
In 8-bit data format, only bits 8–15 of ESCIx_DR need to be accessed.
When transmitting in 9-bit data format and using 8-bit write instructions,
write first to ESCIx_DR[0–7], then ESCIx_DR[8–15]. For 9-bit
transmissions, a single write can also be used.
Do not use ESCIx_DR in LIN mode, writes to this register are blocked in
LIN mode.
Even if parity generation/checking is enabled via ESCIx_CR[PE], the parity
bit is not masked out.
21.3.3.4 eSCI Status Register (ESCIx_SR)
The ESCIx_SR indicates the current status. The status flags can be polled, and some can also be used to
generate interrupts. All bits in ESCIx_SR except for RAF are cleared by writing 1 to them.
Table 21-5. ESCIx_DR Field Description
Field Description
0
R8
Received bit 8. R8 is the ninth data bit received when the eSCI is configured for 9-bit data format (M = 1).
1
T8
Transmit bit 8. T8 is the ninth data bit transmitted when the eSCI is configured for 9-bit data format (M = 1).
Note: If the value of T8 is the same as in the previous transmission, T8 does not have to be rewritten.The same value
is transmitted until T8 is rewritten.
2–7 Reserved.
8–15
R7–R0
T7–T0
Received bits/transmit bits 7–0 for 9-bit or 8-bit formats. Bits 7–0 from SCI communication can be read from
ESCIx_DR[8–15] (provided that SCI communication was successful). Writing to ESCIx_DR [8–15] provides bits 7–0
for SCI transmission.
Address: Base + 0x0008 Access: R/W1c
01 2 3456789101112131415
R TDRE TC RDRF IDLE OR NF FE PF 0 0 0 BERR 0 0 0 RAF
W w1c w1c w1c w1c w1c w1c w1c w1c w1c
Reset11 0 0000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
RRX
RDY
TX
RDY
LWAKE STO
PB
ERR
CERR
CK
ERR
FRC0000000OVFL
W
w1c w1c w1c w1c w1c w1c w1c w1c w1c
Reset00 0 0000000000000
Figure 21-5. eSCI Status Register (ESCIx_SR)
To Next Page
Loading...
