NXP Semiconductors MPC5566 - Bus Interface

MPC5566 Microcontroller Reference Manual, Rev. 2
22-34 Freescale Semiconductor
22.4.8 Bus Interface
The CPU access to FlexCAN2 registers are subject to the following rules:
• Read and write access to unimplemented or reserved address space also results in access error. Any
access to unimplemented MB locations results in access error.
• For a FlexCAN2 configuration that uses less than the total number of MBs and MAXMB is set
accordingly, the remaining MB and RX mask register memory can be used as general-purpose
RAM space. Byte, word and long word accesses are allowed to the unused MB space.
NOTE
Unused MB space must not be used as general purpose RAM while
FlexCAN is transmitting and receiving CAN frames.
22.5 Initialization and Application Information
This section provides instructions for initializing the FlexCAN2 module.
22.5.1 FlexCAN2 Initialization Sequence
The FlexCAN2 module can be reset in three ways:
• MCU-level hard reset, which resets all memory mapped registers asynchronously
• MCU-level soft reset, which resets some of the memory mapped registers synchronously
(see Table 22-2 for the registers affected by a soft reset)
• SOFTRST bit in CANx_MCR, which has the same effect as the MCU level soft reset
A soft reset is synchronous and must follow an internal request/acknowledge procedure across clock
domains. Therefore, it can take some time to fully propagate its effects. The SOFTRST bit remains
asserted while a soft reset is pending, so software can poll this bit to determine when the reset completes.
After the module is enabled (CANx_MCR[MDIS] bit negated), put FlexCAN2 in freeze mode before
beginning the configuration. In freeze mode, FlexCAN2 is un-synchronized to the CAN bus, the HALT
and FRZ bits in CANx_MCR are set, the internal state machines are disabled and the FRZACK and
NOTRDY bits in the CANx_MCR are set. The CNTX pin is in recessive state and FlexCAN2 does not
initiate frame transmission nor receives any frames from the CAN bus. The message buffer contents are
not affected by reset, therefore are not automatically initialized.
For any configuration change or initialization, FlexCAN2 must be set to freeze mode
(see Section 22.4.6.1, “Freeze Mode). A generic initialization process for the FlexCAN2 module is:
1. Initialize CANx_CR.
— Determine bit timing parameters: PROPSEG, PSEG1, PSEG2, RJW.
— Determine the bit rate by programming the PRESDIV field.
— Determine internal arbitration mode (LBUF bit).
2. Initialize message buffers.
— The control and status word of all message buffers can be written as active or inactive.
— Initialize other entries in each message buffer as required.