NXP Semiconductors MPC5566 - Pad Configuration Registers 49 (SIU_PCR49)

System Integration Unit (SIU)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 6-31
6.3.1.25 Pad Configuration Registers 49 (SIU_PCR49)
The SIU_PCR49 register controls the function, direction, and electrical attributes of
DATA[21]_FEC_RX_ER_GPIO[49].
Figure 6-26. DATA[21]_FEC_RX_ER_GPIO[49] Pad Configuration Registers (SIU_PCR49)
Refer to Table 6-19 for bit field definitions. Table 6-26 lists the PA fields for
DATA[21]_FEC_RX_ER_GPIO[49].
6.3.1.26 Pad Configuration Registers 50 (SIU_PCR50)
The SIU_PCR50 register controls the function, direction, and electrical attributes of
DATA[22]_FEC_RXD[0]_GPIO[50].
Figure 6-27. DATA[22]_FEC_RXD[0]_GPIO[50] Pad Configuration Registers (SIU_PCR50)
Address: Base + 0x00A2 Access: R/W
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0
PA OBE
1
1
When configured as DATA[21] or FEC_RX_ER, the OBE bit has no effect.
When configured as GPDO (output), set the OBE bit to 1.
IBE
2
2
When the pad is configured as an output, set the IBE bit to 1 to show the pin state in the GPDI register. Clear the IBE bit to 0
to reduce power consumption. When configured as GPDI, set the IBE bit to 1.
DSC ODE
3
3
When configured as DATA[21] or FEC_RX_ER, clear the ODE bit to 0.
HYS
4
4
If external master operation is enabled, clear the HYS bit to 0.
0 0
WPE
5
5
Refer to the EBI section for weak pullup settings when configured as DATA[21] or FEC_RX_ER.
WPS
5
W
RESET: 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1
Table 6-26. PCR49 PA Field Descriptions
PA Field Pin Function
0b00 GPIO[49]
0b01 DATA[21]
0b10 FEC_RX_ER
0b11 DATA[21]
Address: Base + 0x00A4 Access: R/W
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0
PA OBE
1
1
When configured as DATA[22] FEC_RXD[0], the OBE bit has no effect. When configured as GPDO, set the OBE bit to 1.
IBE
2
2
When the pad is configured as an output, set the IBE bit to 1 to show the pin state in the GPDI register. Clear the IBE bit to 0
to reduce power consumption. When configured as GPDI, set the IBE bit to 1.
DSC ODE
3
3
When configured as DATA[22]FEC_RXD[0], clear the ODE bit to 0.
HYS
4
4
If external master operation is enabled, clear the HYS bit to 0.
0 0
WPE
5
5
Refer to the EBI section for weak pullup settings when configured as DATA[22] FEC_RXD[0].
WPS
5
W
RESET: 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1