NXP Semiconductors MPC5566 - Interrupt Flags High Register (Canx_Ifrh)

MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 22-23
22.3.3.10 Interrupt Flags High Register (CANx_IFRH)
CANx_IFRH defines the flags for 32 message buffer interrupts. It contains one interrupt flag bit per buffer.
Each successful transmission or reception sets the corresponding IFRH bit. If the corresponding IMRH bit
is set, an interrupt is generated. Write a 1 to the interrupt flag to clear its value to zero. Writing a 0 has no
effect.
Address: Base + 0x0028 Access: User R/W
0123456789101112131415
R
BUF
31M
BUF
30M
BUF
29M
BUF
28M
BUF
27M
BUF
26M
BUF
25M
BUF
24M
BUF
23M
BUF
22M
BUF
21M
BUF
20M
BUF
19M
BUF
18M
BUF
17M
BUF
16M
W
Reset0000000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
BUF
15M
BUF
14M
BUF
13M
BUF
12M
BUF
11M
BUF
10M
BUF
09M
BUF
08M
BUF
07M
BUF
06M
BUF
05M
BUF
04M
BUF
03M
BUF
02M
BUF
01M
BUF
00M
W
Reset0000000000000000
Figure 22-11. Interrupt Masks Low Register (CANx_IMRL)
Table 22-14. CANx_IMRL Field Descriptions
Field Description
0–31
BUFnM
Message buffer n mask. Enables or disables the respective FlexCAN2 message buffer (MB31 to MB0)
Interrupt.
0 The corresponding buffer Interrupt is disabled
1 The corresponding buffer Interrupt is enabled
Note: Setting or clearing a bit in the IMRL register can assert or negate an interrupt request, respectively.
Address: Base + 0x002C Access: User R/W1c
0123456789101112131415
RBUF
63I
BUF
62I
BUF
61I
BUF
60I
BUF
59I
BUF
58I
BUF
57I
BUF
56I
BUF
55I
BUF
54I
BUF
53I
BUF
52I
BUF
51I
BUF
50I
BUF
49I
BUF
48I
Ww1cw1cw1cw1cw1cw1cw1cw1cw1cw1cw1cw1cw1cw1cw1cw1c
Reset0000000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
RBUF
47I
BUF
46I
BUF
45I
BUF
44I
BUF
43I
BUF
42I
BUF
41I
BUF
40I
BUF
39I
BUF
38I
BUF
37I
BUF
36I
BUF
35I
BUF
34I
BUF
33I
BUF
32I
Ww1cw1cw1cw1cw1cw1cw1cw1cw1cw1cw1cw1cw1cw1cw1cw1c
Reset0000000000000000
Figure 22-12. Interrupt Flags High Register (CANx_IFRH)