NXP Semiconductors MPC5566 - Configurable Bus Speed Clock Modes

External Bus Interface (EBI)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 12-25
12.4.1.14 Configurable Bus Speed Clock Modes
The EBI supports configurable bus speed clock modes. See Section 12.1.4.4, “Configurable Bus Speed
Modes,” for more details on this feature.
12.4.1.15 Stop and Module Disable Modes for Power Savings
See Section 12.1.4, “Modes of Operation,” for a description of the power saving modes.
12.4.1.16 Optional Automatic CLKOUT Gating
The EBI has the ability to hold the external CLKOUT pin high when the EBI internal master state machine
is idle and no requests are pending. The EBI outputs a signal to the pads logic in the MCU to disable
CLKOUT. This feature is disabled out of reset, and can be enabled or disabled by the ACGE bit in the
EBI_MCR.
NOTE
This feature must be disabled for multi-master systems. In those cases, one
master is getting its clock source from the other master and needs the other
master to stay valid continuously.
12.4.1.17 Compatible with MPC5xx External Bus
(with Some Limitations)
The EBI is compatible with the external bus of the MPC5xx parts, meaning that it supports most devices
supported by the MPC5xx family of parts. However, there are some differences between this EBI and that
of the MPC5xx parts that the user needs to be aware of before assuming that an MPC5xx-compatible
device works with this EBI. See Section 12.5.5, “Summary of Differences from MPC5xx,” for details.
Table 12-13. Write/Byte Enable Signal Functions
Transfer
Size
TSIZ[0:1]
Address 32-Bit 16-Bit
1
1
Also applies when DBM = 1 for 16-bit data bus mode.
A30 A31
WE/BE[0] WE/BE[1] WE/BE[2] WE/BE[3] WE/BE[0] WE/BE[1] WE/BE[2] WE/BE[3]
Byte 01 0 0 X — — — X — — —
01 0 1 — X — — — X — —
01 1 0 — — X — X — — —
01 1 1 — — — X X — —
16-bit 10 0 0 X X — — X X — —
10 1 0 — — X X X X — —
32-bit 00 0 0 X X X X X
2
2
This case consists of two 16-bit external transactions, but for both transactions the WE/BE[0:1] signals are the only WE/BE
signals affected.
NOTE: “X” indicates that valid data is transferred on these bits.
X
2
——
Burst 00 0 0 X X X X X X — —