NXP Semiconductors MPC5566 - Pad Configuration Register 208 (SIU_PCR208)

System Integration Unit (SIU)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 6-89
6.3.1.116 Pad Configuration Register 208 (SIU_PCR208)
The SIU_PCR208 register controls the function, direction, and electrical attributes of
PLLCFG[0]_IRQ[4]_GPIO[208].
Figure 6-117. PLLCFG[0]_IRQ[4]_GPIO[208] Pad Configuration Register (SIU_PCR208)
Refer to Table 6-19 for bit field definitions. Table 6-114 lists the PA fields for
PLLCFG[0]_IRQ[4]_GPIO[208].
6.3.1.117 Pad Configuration Register 209 (SIU_PCR209)
The SIU_PCR209 register controls the function, direction, and electrical attributes of
PLLCFG[1]_IRQ[5]_SOUTD_GPIO[209].
Figure 6-118. PLLCFG[1]_IRQ[5]_SOUTD_GPIO[209] Pad Configuration Register (SIU_PCR209)
Address: Base + 0x01E0 Access: R/W
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0
PA
1
1
The PLLCFG[0] function applies only during reset when the RSTCFG pin is asserted. Set the PA field to 0b10 for IRQ[4], or
to 0b00 for GPIO[208].
OBE
2
2
When configured as IRQ[4], the OBE bit has no effect. When configured as GPDO, set the OBE bit to 1.
IBE
3
3
When the pad is configured as an output, set the IBE bit to 1 to show the pin state in the GPDI register. Clear the IBE bit to 0
to reduce power consumption. When configured as GPDI, set the IBE bit to 1.
0 0
ODE HYS
4
4
When configured as IRQ[4], set the HYS bit to 1.
SRC WPE WPS
W
RESET: 0 0 0 0 1 1 0 0 0 0 0 1 0 0 1 1
Table 6-114. PCR208 PA Field Definitions
PA Field Pin Function
0b00 GPIO[208]
0b01 PLLCFG[0]
0b10 IRQ[4]
0b11 PLLCFG[0]
Address: Base + 0x01E2 Access: R/W
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0
PA
1
1
The PLLCFG[1] function applies only during reset when the RSTCFG pin is asserted during reset. Set the PA field to 0b010
for IRQ
[5], 0b100 for SOUTD, and 0b000 for GPIO[209].
OBE
2
2
When configured as IRQ[5], the OBE bit has no effect. When configured as GPDO, set the OBE bit to 1.
IBE
3
3
When the pad is configured as an output, set the IBE bit to 1 to show the pin state in the GPDI register. Clear the IBE bit to 0
to reduce power consumption. When configured as GPDI, set the IBE bit to 1.
0 0
ODE HYS
4
4
When configured as IRQ[5], set the HYS bit to 1.
SRC WPE WPS
W
RESET: 0 0 0 0 1 1 0 0 0 0 0 1 0 0 1 1