NXP Semiconductors MPC5566 - FLASH_BIUAPR Modification

Flash Memory
MPC5566 Microcontroller Reference Manual, Rev. 2
13-36 Freescale Semiconductor
13.4.2.6.3 FLASH_BIUAPR Modification
Censorship logic prevents modification of the access protection register (FLASH_BIUAPR) bit fields
associated with all masters except the core according to the logic presented in Table 13-18.
13.4.2.6.4 External Boot Default
The SIU latches the boot default value in the SIU_RSR BOOTCFG[0:1] bits if and only if RSTCFG
is
negated. Censorship logic sets the boot default value before the SIU latches the value to
external-with-external-master access disabled (EXTM = 0) if the lower half of the censorship control word
equals 0xFFFF or 0x0000. Otherwise, censorship logic sets the boot default value to internal flash.
13.4.3 Flash Memory Array: Stop Mode
Stop mode is entered by setting the FLASH_MCR[STOP] bit. The FLASH_MCR[STOP] bit cannot be
written when FLASH_MCR[PGM] = 1 or FLASH_MCR[ERS] = 1. In stop mode all DC current sources
in the flash module are disabled. Stop mode is exited by clearing the FLASH_MCR[STOP] bit.
Table 13-18. PFBAPR Modification Logic
BOOTCFG
1
1
BOOTCFG[0:1] bits are located in the SIU_RSR.
Censorship Control Word
EXTM
2
2
EXTM bit is located in the EBI_MCR.
PFBAPR Bitfields
Writable
[0] [1] Upper Half Lower Half
0 0 0x55AA 0xXXXX 0 Yes
0 0 !0x55AA 0xXXXX 0 Yes
1 0 0x55AA 0xXXXX 0 Yes
1 0 !0x55AA 0xXXXX 0 Yes
1 1 0x55AA 0xXXXX 0 Yes
1 1 !0x55AA 0xXXXX 0 Yes
0 1 0xXXXX 0x55AA 0 Yes
0 1 0xXXXX !0x55AA 0 Yes
0 0 0x55AA 0xXXXX 1 Yes
0 0 !0x55AA 0xXXXX 1 No
1 0 0x55AA 0xXXXX 1 Yes
1 0 !0x55AA 0xXXXX 1 No
1 1 0x55AA 0xXXXX 1 Yes
1 1 !0x55AA 0xXXXX 1 No
0 1 0xXXXX 0x55AA 1 No
0 1 0xXXXX !0x55AA 1 No