NXP Semiconductors MPC5566 - Time Base Clock Signal (TCRCLKA and TCRCLKB)

Enhanced Time Processing Unit (eTPU)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 18-13
18.3.2.1 Time Base Clock Signal (TCRCLKA and TCRCLKB)
The TCRCLKA and TCRCLKB input signals are used to control the TCR1 and TCR2 time bases for eTPU
A and eTPU B.
NOTE
Throughout this document, TCRCLKA and TCRCLKB are referred to
generically as TCRCLK.
There is an independent TCRCLK input for each eTPU engine. Table 18-2 shows the TCRCLK pin
connections.
• For pulse accumulator operations, TCRCLK can be used as a gate for a counter based on the system
clock divided by eight.
• For angle operations TCRCLK can be used to get the tooth transition indications in angle mode.
Refer to the eTPU Reference Manual’s Sections 5.9 and 5.10.
18.3.2.2 Channel Output Disable Signals
Each eTPU engine has four input signals that are used to force the outputs of a group of eight channels to
an inactive level. These signals originate from the eMIOS. When an output disable signal is active, all eight
channels assigned to the disable signal that have their ODIS bits set to one in the ETPU_CnCR register
have their outputs forced to the opposite of the value specified in the ETPU_CnCR[OPOL] bit. Therefore,
individual channels can be selected to be affected by the output disable signals, as well as their disabling
forced polarity.
Refer to Section 17.2.1.1, “Output Disable Input—eMIOS Output Disable Input Signals,” for more
information on the output disable signals.
Table 18-2. MPC5566 TCRCLK Signals
Signal Name Pin Assignment I/O
Pin Connection
496 BGA 416 BGA
TCRCLKA_
IRQ
[7]_
GPIO[113]
Primary
Alternate
General-purpose I/O
I
I
I/O
N5 N4
TCRCLKB_
IRQ
[6]_
GPIO[146]
Primary
Alternate
General-purpose I/O
I
I
I/O
K21 M23