NXP Semiconductors MPC5566 - Pad Configuration Register 114-117 (SIU_PCR114-SIU_PCR117)

System Integration Unit (SIU)
MPC5566 Microcontroller Reference Manual, Rev. 2
6-64 Freescale Semiconductor
Refer to Table 6-19 for bit field definitions. Table 6-78 lists the PA fields for
TCRCLKA_IRQ[7]_GPIO[113].
6.3.1.79 Pad Configuration Register 114–117 (SIU_PCR114–SIU_PCR117)
The SIU_PCR114–SIU_PCR117 registers control the function, direction, and electrical attributes of
ETPUA[0:3]_ETPUA[12:15]_GPIO[114:117]. Only the output channels of ETPUA[12:15] are
connected. Both the input and output channels of ETPUA[0:3] are connected.
Figure 6-80. ETPUA[0:3]_ETPUA[12:15]_GPIO[114:117]
Pad Configuration Register (SIU_PCR114–SIU_PCR117)
Refer to Table 6-19 for bit field definitions. Table 6-79 lists the PA fields for
ETPUA[0:3]_ETPUA[12:15]_GPIO[114:117].
Table 6-78. PCR113 PA Field Definitions
PA Field Pin Function
0b00 GPIO[113]
0b01 TCRCLKA
0b10 IRQ[7]
0b11 TCRCLKA
Address: Base + (0x0124–0x012A) Access: R/W
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0
PA OBE
1
1
The OBE bit must be set to 1 for ETPUA[0:3], and GPIO[114:117] when configured as outputs. When configured as
ETPUA[12:15], the OBE bit has no effect.
IBE
2
2
The IBE bit must be set to 1 for ETPUA[0:3] or GPIO[114:117] when configured as inputs. When the pad is configured as an
output, set the IBE bit to 1 to show the pin state in the GPDI register.
0 0
ODE HYS SRC WPE WPS
W
RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 U
3
3
The weak pullup/down selection at reset for the ETPUA[0:3] pin is determined by the WKPCFG pin.
Table 6-79. PCR114–PCR117 PA Field Definitions
PA Field Pin Function
0b00 GPIO[114:117]
0b01 ETPUA[0:3]
0b10 ETPUA[12:15]
0b11 ETPUA[0:3]