EasyManua.ls Logo

NXP Semiconductors MPC5566 - Initialization of On-Chip Adcs and an External Device

NXP Semiconductors MPC5566
1268 pages
To Next Page IconTo Next Page
To Next Page IconTo Next Page
To Previous Page IconTo Previous Page
To Previous Page IconTo Previous Page
Loading...
Enhanced Queued Analog-to-Digital Converter (eQADC)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 19-109
19.5.1.1 Initialization of On-Chip ADCs and an External Device
The following steps provide an example of configuring the eQADC to initialize the on-chip ADCs and the
external device. In this example, commands are sent through CFIFO0.
1. Load all required configuration commands in the RAM in such way that they form a queue; this
data structure is referred to below as Queue0. Figure 19-64 shows an example of a command queue
able to configure the on-chip ADCs and external device at the same time.
2. Configure Section 19.3.2.2, “eQADC Null Message Send Format Register (EQADC_NMSFR).”
3. Configure Section 19.3.2.12, “eQADC SSI Control Register (EQADC_SSICR),” to communicate
with the external device.
4. Enable the eQADC SSI by programming the ESSIE field the Section 19.3.2.1, “eQADC Module
Configuration Register (EQADC_MCR).”
a) Write 0b10 to ESSIE field to enable the eQADC SSI. FCK is free running but serial
transmissions are not started.
b) Wait until the external device becomes stable after reset.
c) Write 0b11 to ESSIE field to enable the eQADC SSI to start serial transmissions.
5. Configure the eDMA to transfer data from Queue0 to CFIFO0 in the eQADC.
6. Configure Section 19.3.2.7, “eQADC Interrupt and eDMA Control Registers 0–5
(EQADC_IDCRn).”
a) Set CFFS0 to configure the eQADC to generate an eDMA request to load commands from
Queue0 to the CFIFO0.
b) Set CFFE0 to enable the eQADC to generate an eDMA request to transfer commands from
Queue0 to CFIFO0; Command transfers from the RAM to the CFIFO0 starts immediately.
c) Set EOQIE0 to enable the eQADC to generate an interrupt after transferring all of the
commands of Queue0 through CFIFO0.
7. Configure Section 19.3.2.6, “eQADC CFIFO Control Registers 0–5 (EQADC_CFCRn).”
a) Write 0b0001 to the MODE0 field in eQADC_CFCR0 to program CFIFO0 for software
single-scan mode.
b) Write 1 to SSE0 to assert SSS0 and trigger CFIFO0.
8. Because CFIFO0 is in single-scan software mode and it is also the highest priority CFIFO, the
eQADC starts to transfer configuration commands to the on-chip ADCs and to the external device.
4 Repetitive
angle-based queue
Every 625 μs 7 Airflow read every 30
degrees at 8000 RPM
5 Slow repetitive
time-based queue
Every 100 ms 10 Temperature sensors
Table 19-56. Example Applications of Each Command Queue (continued)
Command
Queue Number
Queue Type Running Speed
Number of
Contiguous
Conversions
Example

Table of Contents

Related product manuals