Frequency Modulated Phase Locked Loop and System Clocks (FMPLL)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 11-11
NOTE
In addition to supplying power for the CLKOUT signal, when the FMPLL
is configured for external reference mode of operation, the V
DDE5
supply
voltage also controls the voltage level at which the signal presented to the
EXTAL_EXTCLK pin causes a switch in the clock logic levels. The
EXTAL_EXTCLK accepts a clock source with a voltage range of 1.6–3.6 V,
however the transition voltage is determined by V
DDE5
supply voltage
divided by two. As an example, if V
DDE5
is 3.3 V, then the clock transitions
at approximately 1.6 V. The V
DDE5
supply voltage and the voltage level of
the external clock reference must be compatible, or the device does not
clock properly.
11.1.4.3 Bypass Mode
In FMPLL bypass mode, the FMPLL is completely bypassed and the user must supply an external clock
on the EXTAL_EXTCLK pin. The external clock is used directly to produce the internal system clocks.
In bypass mode, the analog portion of the FMPLL is disabled and no clocks are generated at the FMPLL
output. Consequently, frequency modulation is not available. In bypass mode the pre-divider is bypassed
and has no effect on the system clock. The frequency in bypass mode is F
ref_ext
.
To enter bypass mode, the default FMPLL configuration must be overridden by following the procedure
outlined in Section 11.1.4, “FMPLL Modes of Operation.” A block diagram illustrating bypass mode is
shown in Figure 11-2.
11.1.4.4 Dual-Controller Mode (1:1)
FMPLL dual-controller mode is used by the slave MCU device of a dual-controller system. The slave
FMPLL facilitates skew reduction between the input and output clock signals. To enter dual-controller
mode, the default FMPLL configuration must be overridden by the procedure outlined in Section 11.1.4,
“FMPLL Modes of Operation.”
In this mode, the system clock runs at twice the frequency of the EXTAL_EXTCLK input pin and is phase
aligned. Note that crystal operation is not supported in dual-controller mode and an external clock must be
provided. In this mode, the frequency and phase of the signal at the EXTAL_EXTCLK pin and the
CLKOUT pin of the slave MCU are matched. A block diagram illustrating dual-controller mode (1:1) is
shown in Figure 11-6.
Frequency modulation is not available when configured for dual-controller mode for both the master and
slave devices. Enabling frequency modulation on the device supplying the reference clock to the slave in
dual-controller mode produces unreliable clocks on the slave.
NOTE
When configured for dual-controller mode, the CLKOUT clock divider on
the slave device must not be changed from its reset state of divide-by-two.
Increasing or decreasing this divide ratio produces unpredictable results
from the FMPLL.
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