Introduction
MPC5566 Microcontroller Reference Manual, Rev. 2
1-14 Freescale Semiconductor
The CPU includes support for Variable Length Encoding (VLE) instruction enhancements that have
modified instruction set that uses a combination of 16- and 32-bit instructions from the classic Power
Architecture instruction. This reduces the code size without noticeably affecting performance. The classic
Power Architecture instruction set and VLE instruction set are available concurrently. Regions of the
memory map are designated as PPC or VLE using an additional configuration bit in each table look-aside
buffer (TLB) entry in the MMU.
1.5.2 System Bus Crossbar Switch (XBAR)
The system bus’ multi-port crossbar (XBAR) switch supports simultaneous connections between four
master ports and five slave ports. The crossbar supports a 32-bit address bus width and a 64-bit data bus
width on all master and slave ports.
The crossbar allows concurrent transactions from any master port to any slave port. It is possible to use all
master ports and slave ports at the same time as a result of independent master requests. If a slave port is
simultaneously requested by more than one master port, arbitration logic selects the highest priority master
and grants it ownership of the slave port. All other masters requesting that slave port must wait until the
higher priority master completes its transactions. By default, masters requests’ have equal priority and are
granted access to a slave port in round-robin fashion based on the last master ID granted access.
1.5.3 Enhanced Direct Memory Access (eDMA)
The enhanced direct memory access (eDMA) controller is a second-generation module capable of
performing complex data movements via 64 programmable channels, with minimal intervention from the
CPU. The hardware microarchitecture includes a DMA engine which performs source and destination
address calculations, and the actual data movement operations, along with an SRAM-based memory
containing the transfer control descriptors (TCD) for the channels. This implementation is used to
minimize the overall module size.
1.5.4 Interrupt Controller (INTC)
The interrupt controller (INTC) provides priority-based preemptive scheduling of interrupt requests,
suitable for statically scheduled real-time systems. The INTC allows interrupt request servicing from
329
1
total interrupt vectors.
For high-priority interrupt requests, the time from when the peripheral interrupt request asserts to when
the processor executes the interrupt service routine (ISR) is minimized. A unique vector for each interrupt
request source is used to quickly determine which ISR to execute. The INTC module provides a number
of priorities to ensure that lower priority ISRs do not delay the execution of higher priority ISRs. Software
is used to configure the interrupt priorities for each interrupt source.
When multiple tasks share a resource, coherent accesses to that resource must be supported. The INTC
supports the priority ceiling protocol for coherent accesses. By providing a modifiable priority mask, the
1. Although this device has a maximum of 329 interrupts, the logic requires that the total number of interrupts be divisible by four.
Therefore, the total number of interrupts specified for this device is 332.
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