NXP Semiconductors MPC5566 - Transfer Control Descriptor (TCD)

Enhanced Direct Memory Access (eDMA)
MPC5566 Microcontroller Reference Manual, Rev. 2
9-24 Freescale Semiconductor
9.2.2.17 Transfer Control Descriptor (TCD)
Each channel requires a 256-bit transfer control descriptor for defining the desired data movement
operation. The channel descriptors are stored in the local memory in sequential order: channel 0,
channel 1,... channel 63. The definitions of the TCD are presented as 23 variable-length fields.
2–3
GRPPRI
[0:1]
Channel n current group priority. Group priority assigned to this channel group when fixed-priority
arbitration is enabled. These two bits are read only; writes are ignored. The reset value for the group
priority fields, is equal to the corresponding channel number for each priority register; that is,
EDMA_CPR31[GRPPRI] = 0b01.
4–7
CHPRI
[0:3]
Channel n arbitration priority. Channel priority when fixed-priority arbitration is enabled. The reset value
for the channel priority fields CHPRI[0–3], is equal to the corresponding channel number for each priority
register; that is, EDMA_CPR31[CHPRI] = 0b1111.
Table 9-17. EDMA_CPRn Field Descriptions (continued)
Field Description