e200z6 Core Complex
MPC5566 Microcontroller Reference Manual, Rev. 2
3-4 Freescale Semiconductor
• Signal processing extension APU supporting fixed-point and single-precision floating-point
operations, using the 64-bit general-purpose register file
• Nexus class 3 real-time development unit
• Power management
— Low-power design
— Dynamic power management of execution units, caches, and MMUs
3.1.3.1 Instruction Unit Features
The features of the instruction unit are the following:
• 64-bit path to cache supports fetching of two 32-bit instructions per clock, or up to
four 16-bit VLE APU instructions per clock
• Instruction buffer holds up to six sequential instructions
• Dedicated PC incrementer supporting instruction prefetches
• Branch target address cache with dedicated branch address adder, and branch lookahead logic
supporting single cycle execution of successful lookahead branches
3.1.3.2 Integer Unit Features
The integer unit supports single-cycle execution of most integer instructions:
• 32-bit AU for arithmetic and comparison operations
• 32-bit LU for logical operations
• 32-bit priority encoder for count leading zeros function
• 32-bit single cycle barrel shifter for static shifts and rotates
• 32-bit mask unit for data masking and insertion
• Divider logic for signed and unsigned divides in 6–16 clocks with minimized execution timing
• Pipelined 32x32 hardware multiplier array supports 32x32->32 multiply with three clock latency,
one clock throughput
3.1.3.3 Load/Store Unit Features
The load/store unit supports load, store, and the load multiple/store multiple instructions:
• 32-bit effective address adder for data memory address calculations
• Pipelined operation supports throughput of one load or store operation per cycle
• Dedicated 64-bit interface to memory supports saving and restoring of up to two registers per cycle
for load multiple and store multiple word instructions
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