NXP Semiconductors MPC5566 - Memory Map and Register Definition

Enhanced Time Processing Unit (eTPU)
MPC5566 Microcontroller Reference Manual, Rev. 2
18-14 Freescale Semiconductor
The output disable channel groups are defined in Table 18-3.
18.4 Memory Map and Register Definition
18.4.1 eTPU Memory Map Overview
The eTPU system simplified memory map is shown in Table 18-4. The base address for the eTPU module
is listed as BASE. Each of the register areas shown can have their own reserved address areas.
Table 18-3. Output Disable Channel Groups
eMIOS Channel Engine eTPU Channels Disabled
11
A
0–7
10 8–15
9 16–23
8 24–31
20
B
0–7
21 8–15
22 16–23
23 24–31
Table 18-4. eTPU High-Level Memory Map
Address Register Description
Base (C3FC_0000)–
Base + 0x0000_001F
eTPU system module configuration registers
Base + (0x0000_0020–0x0000_002F) eTPU A time base registers
Base + (0x0000_0030–0x0000_003F) Reserved
Base + (0x0000_0040–0x0000_004F) eTPU B time base registers
Base + (0x0000_0050–0x0000_01FF) Reserved
Base + (0x0000_0200–0x0000_02FF) eTPU A and B global channel registers
Base + (0x0000_0300–0x0000_03FF) Reserved
Base + (0x0000_0400–0x0000_07FF) eTPU A channel registers
Base + (0x0000_0800–0x0000_0BFF) eTPU B channel registers
Base + (0x0000_0C00–0x0000_7FFF) Reserved
Base + (0x0000_8000–0x0000_8FFF) Shared data memory (4 KB)
Base + (0x0000_9000–0x0000_BFFF) Reserved
Base + (0x0000_C000–0x0000_CFFF) Shared data memory PSE mirror
1
(4 KB)
Base + (0x0000_CD00–0x0000_FFFF) Reserved