NXP Semiconductors MPC5566 - Chapter 5 Ripheral Access Control Registers (Pbridge_X_Opacr)

Peripheral Bridge (PBRIDGE A and PBRIDGE B)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 5-7
5.3.1.2 Peripheral Access Control Registers (PBRIDGE_x_PACR) and
Off-Platform Peripheral Access Control Registers (PBRIDGE_x_OPACR)
Each of the PBRIDGE on-platform peripherals has a 4-bit access field in a peripheral access control
register (PACR) that defines the access levels supported by the given module. A single PACR contains up
to eight of these module-access fields, and the PACR register structure is shown in Table 5-2 and
Table 5-3. The PACR registers with their access fields are shown in Figure 5-3. There are three PACR
registers, one for bridge A and two for bridge B.
Also, each of the off-platform peripherals has a 4-bit access field in an off-platform peripheral access
control register (PBRIDGE_x_OPACR) that defines the access levels supported by the given module.
Each OPACR contains up to eight of these module-access fields, and the OPACR register structure is
shown in Table 5-2 and Table 5-3. The OPACR registers with their access fields are shown in Figure 5-4.
Seven OPACR registers are used, three for bridge A, and four for bridge B.
NOTE
Not all members of the MPC5500 family have PBRIDGE_x_PACR and
PBRIDGE_x_OPACR. On the devices that do not have them, writes to their
addresses receive a transfer error. To ensure code compatibility across all the
MPC55XX family of products, writes to those addresses must be qualified
with SIU_MIDR[PARTNUM].
NOTE
Write PBRIDGE_x_PACR and PBRIDGE_x_OPACR with a
read/modify/write for code compatibility.
16
MBW4
Master buffer writes. Determines whether the PBRIDGE is enabled to buffer writes from the FEC. Writes not
able to be buffered by default.
0 Write accesses from the FEC are not bufferable
1 Write accesses from the FEC are allowed to be buffered
17
MTR4
Master trusted for reads. Determines whether the FEC is trusted for read accesses. Trusted by default.
0 The FEC is not trusted for read accesses.
1 The FEC is trusted for read accesses.
18
MTW4
Master trusted for writes. Determines whether the master is trusted for write accesses. Trusted by default.
0 The FEC is not trusted for write accesses.
1 The FEC is trusted for write accesses.
19
MPL4
Master privilege level. Determines how the privilege level of the FEC is determined. Accesses not forced to
user mode by default.
0 Accesses from the FEC are forced to user mode.
1 Accesses from the FEC are not forced to user mode.
20–31 Reserved.
Table 5-4. PBRIDGE_x_MPCR Field Descriptions (continued)
Field Description