Peripheral Bridge (PBRIDGE A and PBRIDGE B)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 5-9
Address: Base + 0x0040 (PBRIDGE_x_OPACR0);
Base + 0x0044 (PBRIDGE_x_OPACR1);
Base + 0x0048 (PBRIDGE_x_OPACR2);
Base + 0x004C (PBRIDGE_B_OPACR3)
Access: R/W
0 12 3 456789101112131415
RBW0
1
SP0
2
WP0
TP0
2
BW1 SP1 WP1 TP1 BW2 SP2 WP2 TP2 BW3 SP3 WP3 TP3
W
Reset0 10 0 010001000100
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
BW4 SP4 WP4 TP4 BW5 SP5 WP5 TP5 BW6 SP6 WP6 TP6 BW7 SP7 WP7 TP7
W
Reset0 10 0 010001000100
1
In the PBRIDGE_A_PACR0 and PBRIDGE_B_PACR0 registers, the BW0 bit is not writeable
2
The SP0 and TP0 bits default values are always used, even though the bits are writeable.
Figure 5-4. Off-platform Peripheral Access Control Registers (PBRIDGE_x_OPACRn)
Table 5-5. PBRIDGE_x_PACRn and PBRIDGE_x_OPACRn
Field Descriptions
Field Description
0, 4, 8, 12, 16,
20, 24, 28
BWn
Buffer writes. Determines whether write accesses to this peripheral are allowed to be buffered. Write
accesses not bufferable by default
0 No write accesses are bufferable by the PBRIDGE to this peripheral.
1 Write accesses can be buffered by the PBRIDGE to this peripheral.
Note: In PBRIDGE_A_PACR0 and PBRIDGE_B_PACR0, the BW0 bit is not writeable.
1, 5, 9, 13, 17,
21, 25, 29
SPn
Supervisor protect. Determines whether the peripheral requires supervisor privilege level for access.
Supervisor privilege level required by default.
0 The peripheral does not require supervisor privilege level for accesses.
1 The peripheral requires supervisor privilege level for accesses.
The PBRIDGE_x_MPCR[MPLy] control bit for the master must be set. If not, access is terminated
with an error response and no peripheral access is initiated on the slave bus.
Note: For PBRIDGE_A_PACR0 and PBRIDGE_B_PACR0, you must have supervisor privileges to
access PBRIDGE registers.
Note: Even though the SP0 bit (1) is writeable, the reset value for SP0 is always used.
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