NXP Semiconductors MPC5566 - Pad Configuration Registers 55 (SIU_PCR55)

System Integration Unit (SIU)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 6-35
6.3.1.31 Pad Configuration Registers 55 (SIU_PCR55)
The SIU_PCR55 register controls the function, direction, and electrical attributes of
DATA[27]_FEC_TXD[2]_GPIO[55].
Figure 6-32. DATA[27]_FEC_TXD[2]_GPIO[55] Pad Configuration Registers (SIU_PCR55)
Refer to Table 6-19 for bit field definitions. Table 6-32 lists the PA fields for
DATA[27]_FEC_TXD[2]_GPIO[55].
6.3.1.32 Pad Configuration Registers 56 (SIU_PCR56)
The SIU_PCR56 register controls the function, direction, and electrical attributes of
DATA[28]_FEC_TXD[1]_GPIO[56].
Figure 6-33. DATA[28]_FEC_TXD[1]_GPIO[56] Pad Configuration Registers (SIU_PCR56)
Address: Base + 0x00AE Access: R/W
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0
PA OBE
1
1
When configured as DATA[27] or FEC_TXD[2], the OBE bit has no effect.
When configured as GPDO, set the OBE bit to 1.
IBE
2
2
When the pad is configured as an output, set the IBE bit to 1 shows the pin state in the GPDI register. Clear the IBE bit to 0 to
reduce power consumption. When configured as GPDI, set the IBE bit to 1.
DSC ODE
3
3
When configured as DATA[27] or FEC_TXD[2], clear the ODE bit to 0.
HYS
4
4
If external master operation is enabled, clear the HYS bit to 0.
0 0
WPE
5
5
Refer to the EBI section for weak pullup settings when configured as DATA[27] or FEC_TXD[2].
WPS
5
W
RESET: 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1
Table 6-32. PCR55 PA Field Descriptions
PA Field Pin Function
0b00 GPIO[55]
0b01 DATA[27]
0b10 FEC_TXD[2]
0b11 DATA[27]
Address: Base + 0x00B0 Access: R/W
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0
PA OBE
1
1
When configured as DATA[28] or FEC_TXD[1], the OBE bit has no effect.
When configured as GPDO, set the OBE bit to 1.
IBE
2
2
When the pad is configured as an output, set the IBE bit to 1 to show the pin state in the GPDI register.
Clear the IBE bit to 0 to reduce power consumption. When configured as GPDI, set the IBE bit to 1.
DSC ODE
3
3
When configured as DATA[28] or FEC_TXD[1], clear the ODE bit to 0.
HYS
4
4
If external master operation is enabled, clear the HYS bit to 0.
0 0
WPE
5
5
Refer to the EBI section for weak pullup settings when configured as DATA[28] or FEC_TXD[1].
WPS
5
W
RESET: 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1