NXP Semiconductors MPC5566 - Ethernet Control Register (ECR)

Fast Ethernet Controller (FEC)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 15-15
Table 15-7 describes the transmit descriptor active register (TDAR):
15.3.4.2.5 Ethernet Control Register (ECR)
ECR is a read/write application register, though both fields in this register can be altered by hardware as
well. The ECR is used to enable and disable the FEC.
Table 15-8 describes the fields and functions in the Ethernet control register:
Table 15-7. TDAR Field Descriptions
Field Description
0–6 Reserved, must be cleared.
7
X_DES_ACTIVE
Set to one when this register is written, regardless of the value written. Cleared by the FEC device
whenever no additional “ready” descriptors remain in the transmit ring. Also cleared when
ECR[ETHER_EN] is cleared.
8–31 Reserved, must be cleared.
Address: Base + 0x0024 Access: User R/W
0 123456 7 891011121314 15
R0 0000000000000 0 0
W
Reset00000000000000 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R 0000000000 0000
ETHER
EN
RESET
W
Reset00000000000000 0 0
Figure 15-7. Ethernet Control Register (ECR)
Table 15-8. ECR Field Descriptions
Bits Description
0–29 Reserved
30
ETHER_EN
When this bit is set, the FEC is enabled, and reception and transmission are possible. When this bit is
cleared, reception is immediately stopped and transmission is stopped after a bad CRC is appended to
any currently transmitted frame. The buffer descriptors for an aborted transmit frame are not updated
after clearing this bit. When ETHER_EN is deasserted, the DMA, buffer descriptor, and FIFO control
logic are reset, including the buffer descriptor and FIFO pointers. The ETHER_EN bit is altered by
hardware under the following conditions:
• ECR[RESET] is set by software, in which case ETHER_EN is cleared
• An error condition causes the EIR[EBERR] bit to set, in which case ETHER_EN is cleared
31
RESET
When this bit is set, the equivalent of a hardware reset is performed but it is local to the FEC.
ETHER_EN is cleared and all other FEC registers take their reset values. Also, any
transmission/reception currently in progress is abruptly aborted. This bit is automatically cleared by
hardware during the reset sequence. The reset sequence takes approximately 8 system clock cycles
after RESET is written with a 1.