NXP Semiconductors MPC5566 - ECC Error Generation Register (ECSM_EEGR)

Error Correction Status Module (ECSM)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 8-5
The ECSM allows a maximum of one bit of the ECSM_ESR to assert at any given time. This preserves
the association between the ECSM_ESR and the corresponding address and attribute registers, which are
loaded on each occurrence of an correctly-enabled ECC event. If there is a pending ECC interrupt and
another correctly-enabled ECC event occurs, the ECSM hardware automatically performs the
ECSM_ESR reporting by clearing the previous data and loading the new state, which ensures that only a
single flag is asserted.
To maintain the coherent software view of the reported event, use the following sequence in the ECSM
error interrupt service routine:
1. Read the ECSM_ESR and save it.
2. Read and save all the address and attribute reporting registers.
3. Re-read the ECSM_ESR and verify the current contents matches the original contents. If the two
values are different, return to step 1 and repeat this sequence.
4. When the values are identical, write a 1 to the asserted ECSM_ESR flag to negate the interrupt
request.
If multiple status flags are detected simultaneously, the ECSM records the higher priority RAM
non-correctable error (RNCE) events before flash non-correctable error (FNCE) events.
8.2.1.5 ECC Error Generation Register (ECSM_EEGR)
The ECSM_EEGR is a 16-bit control register used to generate double-bit data errors in internal SRAM.
This allows you to test the software service routines for memory error logging.By generating errors during
Base + 0x0047 Access: Read/Write to clear
01234567
R000000RNCEFNCE
W w1c w1c
Reset00000000
Figure 8-2. ECC Status Register (ECSM_ESR)
Table 8-3. ECSM_ESR Field Definitions
Field Description
0–5 Reserved.
6
RNCE
RAM non-correctable error. A non-correctable RAM error 0ccurred. generates an ECSM ECC interrupt request. The
faulting address, attributes and data are also captured in the REAR, REMR, REAT and REDR registers. To clear this
interrupt flag, write a 1 to this bit. Writing a 0 has no effect.
0 No reportable non-correctable RAM error has been detected.
1 A reportable non-correctable RAM error has been detected.
7
FNCE
Flash non-correctable error. The occurrence of a correctly-enabled non-correctable flash error generates an ECSM
ECC interrupt request. The faulting address, attributes and data are also captured in the FEAR, FEMR, FEAT and
FEDR registers. To clear this interrupt flag, write a 1 to this bit. Writing a 0 has no effect.
0 No reportable non-correctable flash error has been detected.
1 A reportable non-correctable flash error has been detected.