Reset
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 4-13
4.4.3.4 PLLCFG[0:1] Pins
The PLLCFG pins are explained in Section 11.1.4, “FMPLL Modes of Operation.”
Refer to Chapter 2, “Signal Description” for information about the PLLCFG pins.
4.4.3.5 Reset Configuration Halfword
4.4.3.5.1 Reset Configuration Halfword Definition
The RCHW is read from either external memory or internal flash memory. If a valid RCHW is not found,
a FlexCAN or eSCI boot is initiated. The RCHW is a collection of control bits that specify a minimum
MCU configuration after reset and define the desired mode of operation of the BAM program. At reset the
RCHW provides a means to locate the boot code, determines if flash memory is programmed or erased,
enables or disables the watchdog timer, configures the MMU to boot as either classic Power Architecture
Book E code or as Freescale VLE code, and if booting externally, sets the bus size. Refer to the register
indicated in RCHW bit descriptions for a description of each control bit.
NOTE
Do not configure the RCHW to a 32-bit bus size for devices with only a
16-bit data bus.
If booting from internal flash or external memory, the application must ensure that RCHW is the correct
value for the configuration, and that it resides in that memory location. The boot ID of the RCHW must
read 0x5A. BOOT_BLOCK_ADDRESS is explained in Section 16.3.2.2.5, “Read the Reset
Configuration Halfword.”
The fields of the RCHW are shown in Figure 4-3.
Figure 4-3. RCHW Fields
Table 4-7. Configurations using PLLCFG[0:1] and RSTCFG
RSTCFG PLLCFG0 PLLCFG1 Clock Mode MODE PLLSEL PLLREF
1 PLLCFG pins ignored Crystal reference (default) 1 1 1
0 0 0 Bypass mode 0 0 0
0 0 1 External reference 1 1 0
0 1 0 Crystal reference 1 1 1
0 1 1 Dual controller mode 1 0 0
BOOT_BLOCK_ADDRESS + 0x0000_0000 Boot Identifier = 0x5A
0123456789101112131415
WTEPS0VLE01011010
5 A
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