Enhanced Queued Analog-to-Digital Converter (eQADC)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 19-107
19.4.9.2.2 RSD Overview
Figure 19-61. RSD Stage Block Diagram
On each pass through the RSD stage, the input signal are multiplied by exactly two, and summed with
either –vref, 0, or vref, depending on the logic control. The logic control determines –vref, 0, or vref,
depending on the two comparator inputs. As the logic control sets the summing operation, it also sends a
digital value to the RSD adder. Each time an analog signal passes through the RSD single-stage, a digital
value is collected by the RSD adder. At the end of an entire AD conversion cycle, the RSD adder uses these
collected values to calculate the 12-bit digital output.
Figure 19-62 shows the transfer function for the RSD stage. Note how the digital value (AB) is dependent
on the two comparator inputs.
Figure 19-62. RSD Stage Transfer Function
In each pass through the RSD stage, the remainder is sent back as the new input, and the digital signals, a
and b, are stored. For the 12-bit ADC, the input signal is sampled during the input phase, and after each of
the 12 passes through the RSD stage. Thus, 13 total a and b values are collected. Upon collecting all these
+
–
Vrefl
Logic
Control
+
–
Vrefh
Digital
Signal
RSD
Adder
–vref,0,vref
Sumx2
Residue VoltageInput Voltage
vref
vref
–vref
–vref VL VH
Input Voltage
Residue Voltage
Vres=2Vin+vref Vres=2Vin Vres=2Vin–vref
a=0, b=0 a=1, b=0
a=0, b=1
To Next Page
Loading...
Need help?
General
