NXP Semiconductors MPC5566 - Baud Rate Generation

Enhanced Serial Communication Interface (eSCI)
MPC5566 Microcontroller Reference Manual, Rev. 2
21-20 Freescale Semiconductor
21.4.3 Baud Rate Generation
A 13-bit modulus counter in the baud rate generator derives the baud rate for both the receiver and the
transmitter. The value, 1 to 8191, written to the SBR0–SBR12 bits determines the system clock divider.
The SBR bits are in the eSCI control register 1 (ESCIx_CR1). The baud rate clock is synchronized with
the system clock and drives the receiver. The baud rate clock divided by 16 drives the transmitter. The
receiver has an acquisition rate of 16 samples per bit time.
Baud rate generation is subject to one source of error when integer division of the system clock does not
result in the exact target frequency.
Table 21-17 lists some examples of achieving target baud rates with a system clock frequency of 128 MHz.
Table 21-17. Baud Rates (Example: System Clock = 128 MHz)
Bits
SBR[0:12]
Receiver
Clock (Hz)
Transmitter
Clock (Hz)
Targ et Bau d
Rate
Error
(%)
0x0023 3,657,143 228,571 230,400 –0.79
0x0045 1,855,072 115,942 115,200 +0.64
0x008B 920,863 57,554 57,600 –0.01
0x00D0 615,385 38,462 38,400 +0.16
0x01A1 306,954 19,185 19,200 –0.08
0x022C 230,216 14,388 14,400 –0.08
0x0341 153,661 9,604 9600 +.04
0x0683 76,785 4,799 4800 –0.02
0x0D05 38,404 2,400.2 2400 +.01
0x1A0A 19,202 1,200.1 1200 +.01
SCI baud rate
System clock
16 ESCIx_CR1[SBR]×
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