NXP Semiconductors MPC5566 - Data Trace End Address Registers 1 and 2 (DTEA1 and DTEA2)

Nexus
MPC5566 Microcontroller Reference Manual, Rev. 2
25-80 Freescale Semiconductor
25.17.2.5 Data Trace End Address Registers 1 and 2 (DTEA1 and DTEA2)
The data trace end address registers define the end addresses for each trace channel.
Table 25-51 illustrates the range that is selected for data trace for various cases of DTSA being less than,
greater than, or equal to DTEA.
NOTE
DTSA must be less than (or equal to) DTEA to guarantee correct data
write/read traces. When the range control bit is 0 (internal range), accesses
to DTSA and DTEA addresses are traced. When the range control bit is 1
(external range), accesses to DTSA and DTEA are not traced.
25.17.2.6 Breakpoint / Watchpoint Control Register 1 (BWC1)
Breakpoint/watchpoint control register 1 controls attributes for generation of NXDM watchpoint
number 1.
Access: R/W
313029282726252423222120191817161514131211109876543210
R
DATA TRACE END ADDRESS
W
Reset00000000000000000000000000000000
Figure 25-60. Data Trace Start Address Registers (DTEA1, DTEA2)
Table 25-51. Data Trace Address Range Options
Programmed Values Range Control Bit Value Range Selected
DTSA < or = DTEA 0 DTSA-> <-DTEA
DTSA < or = DTEA 1 <- DTSA DTEA ->
DTSA > DTEA N/A Invalid range, no trace
Access: R/W
31302928272625242322212019181716 15 14131211109876543210
R
BWE1 BRW1 BWR1 BWT1
W
Reset0000000000000000 0 000000000000000
Figure 25-61. Break / Watchpoint Control Register 1 (BWC1)