NXP Semiconductors MPC5566 - Control Register (Canx_Cr)

MPC5566 Microcontroller Reference Manual, Rev. 2
22-12 Freescale Semiconductor
22.3.3.2 Control Register (CANx_CR)
CANx_CR is defined for specific FlexCAN2 control features related to the CAN bus, such as bit-rate,
programmable sampling point within an RX bit, loop-back mode, listen-only mode, bus off recovery
behavior, and interrupt enabling (for example, bus-off, error). It also determines the division factor for the
clock prescaler. BOFFMSK, ERRMSK, and BOFFREC bits can be accessed at any time. CANx_CR is
unaffected by soft reset, which occurs when CAN_MCR[SOFTRST] is asserted.
14
SRXDIS
This bit defines whether FlexCAN is allowed to receive frames transmitted by itself. If this bit is
asserted, frames transmitted by the module is not stored in any MB, regardless if the MB is
programmed with an ID that matches the transmitted frame, and no interrupt flag or interrupt signal
is generated due to the frame reception.
1 = Self reception disabled
0 = Self reception enabled
15
MBFEN
Message buffer filter enable. This bit provides the capability of enabling either individual masking of every
message buffer, or global masking of message buffers.
By negating MBFEN, global masking is enabled and FlexCAN uses the Rx ID masking scheme of
RXGMASK, RX14MASK and RX15MASK. MB14 and MB15 have individual masks and the others share the
global mask. The scheme does not provide a reception queue; i.e. a received message always fills the first
matching buffer, setting the CODE field to overrun if the buffer contained an unread message. See
Section 22.3.3.4, “RX Mask Registers” for more information. Use global masking for compatibility with
previous FlexCAN versions, which negates MBFEN at reset to retain compatibility with existing software.
By asserting MBFEN, individual Rx ID masking and the reception queue features are enabled. In this
scheme, individual receive mask registers (RXIM[0-63]) are provided for each MB. Upon receiving a
message, FlexCAN searches the reception queue for the first empty matching MB. See Section 22.3.3.5, “RX
Individual Mask Registers (CANx_RXIMR0 through CANx_RXIMR63)” and Section 22.4.3.2, “Reception
Queue” for more information.
0 = Individual RX masking and reception queue features are disabled (thus the device is compatible with
previous FlexCAN versions, i.e. one global mask register is used).
1 = Individual RX masking and reception queue features are enabled.
16–25 Reserved.
26–31
MAXMB[0:5]
Maximum number of message buffers. This 6-bit field defines the maximum number of message buffers of
the FlexCAN2 module. The reset value (0x0F) is equivalent to 16 MB configuration. FlexCAN must be in
freeze mode before changing this value.
Note: MAXMB must be less than or equal to the number of available message buffers. FlexCAN2 cannot
transmit or receive frames if this value is greater than the number of available message buffers.
Table 22-7. CANx_MCR Field Descriptions (continued)
Field Description
Maximum MBs in use MAXMB 1+=