Nexus
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 25-47
25.12.2 OTM Error Messages
An error message occurs when a new message cannot be queued due to the message queue being full. The
FIFO discards incoming messages until the queue the queue is completely empty. After it empties, an error
message is queued. The error encoding indicate the message types denied service to the queue while the
FIFO was emptying.
If an OTM message only attempts to enter the queue while the queue is emptying, the error message
incorporates the OTM error encoding (00000) only. If OTM and either BTM or DTM messages attempt to
enter the queue, the error message incorporates the OTM and (program or data) trace error encoding
(00111). If a watchpoint also attempts to enter the queue while the FIFO is emptying, then the error
message incorporates error encoding (01000).
NOTE
The OVC bits within the DC1 register can be set to delay the CPU to
alleviate (but not eliminate) potential overrun situations.
Error information is messaged out in the following format (refer to Table 25-20):
Figure 25-28. Error Message Format
25.12.3 OTM Flow
Ownership trace messages are generated when the operating system writes to the e200z6 process ID
register or the memory mapped ownership trace register.
The following flow describes the OTM process:
1. The process ID register is a system control register. It is internal to the e200z6 processor and can
be accessed by using PPC instructions mtspr and mfspr. The contents of this register are replicated
on the pins of the processor and connected to Nexus.
2. OTR/process ID register reads do not cause ownership trace messages to be transmitted by the
NZ6C3 module.
3. If the periodic OTM message counter expires (after 255 queued messages without an OTM), an
OTM is sent using the latched data from the previous OTM or process ID register write.
25.13 Program Trace
This section details the program trace mechanism supported by NZ6C3 for the e200z6 processor. Program
trace is implemented via branch trace messaging (BTM) as per the Class 3 IEEE®-ISTO 5001-2003
standard definition. Branch trace messaging for e200z6 processors is accomplished by snooping the
e200z6 virtual address bus (between the CPU and MMU), attribute signals, and CPU status.
ECODE (00000 / 00111 / 01000)
MSB LSB
12
SRC TCODE (001000)
3
6 bits4 bits5 bits
Fixed length = 15 bits
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