Enhanced Direct Memory Access (eDMA)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 9-3
• Transfer control descriptor (TCD) organized to support two-deep, nested transfer operations
— 32-byte TCD per channel stored in local memory
— An inner data transfer loop defined by a minor byte transfer count
— An outer data transfer loop defined by a major iteration count
• Channel activation via one of three methods:
— Explicit software initiation
— Initiation via a channel-to-channel linking mechanism for continual transfers
— Peripheral-paced hardware requests (one per channel)
NOTE
For all three methods, one activation per execution of the minor loop is 
required.
• Support for fixed-priority and round-robin channel arbitration
• Support for complex data structures
• Support to cancel transfers via software 
• Channel completion reported via optional interrupt requests
— One interrupt per channel, optionally asserted at completion of major iteration count
— Error terminations are enabled per channel, and logically summed together to form two error 
interrupts
• Support for scatter/gather DMA processing
• Any channel can be programmed so that it can be suspended by a higher priority channel’s 
activation, before completion of a minor loop
Throughout this chapter, n is used to reference the channel number. Additionally, data sizes are defined as 
byte (8-bit), halfword (16-bit), word (32-bit) and doubleword (64-bit).
9.1.2 Modes of Operation
9.1.2.1 Normal Mode
In normal mode, the eDMA is used to transfer data between a source and a destination. The source and 
destination can be a memory block or an I/O block capable of operation with the eDMA.
9.1.2.2 Debug Mode
If enabled by EDMA_CR[EDBG] and the CPU enters debug mode, the eDMA does not grant a service 
request when the debug input signal is asserted. If the signal asserts during a data block transfer as 
described by a minor loop in the current active channel’s TCD, the eDMA continues the operation until 
the minor loop completes.