Deserial Serial Peripheral Interface (DSPI)
MPC5566 Microcontroller Reference Manual, Rev. 2
20-40 Freescale Semiconductor
20.4.3.5.2 Draining the RX FIFO
Host software or the eDMA can remove (pop) entries from the RX FIFO by reading the DSPIx_POPR. A
read of the DSPIx_POPR decrements the RX FIFO counter by one. Attempts to pop data from an empty
RX FIFO are ignored, the RX FIFO counter remains unchanged. The data returned from reading an empty
RX FIFO is undetermined.
See Section 20.3.2.7, “DSPI POP RX FIFO Register (DSPIx_POPR)” for more information on
DSPIx_POPR.
When the RX FIFO is not empty, the RX FIFO drain flag (RFDF) in the DSPIx_SR is set. The RFDF bit
is cleared when the RX_FIFO is empty and the eDMA controller indicates that a read from DSPIx_POPR
is complete; alternatively the RFDF bit can be cleared by the host writing a 1 to it.
20.4.4 Deserial Serial Interface (DSI) Configuration
The DSI configuration supports pin count reduction by serializing parallel input signals or register bits and
shifting them out in an SPI-like protocol. The received serial frames are converted to a parallel form
(deserialized) and placed on the parallel output signals or in a register. The various features of the DSI
configuration are set in the DSPIx_DSICR. For more information on the DSPIx_DSICR. The DSPI is in
DSI configuration when the DCONF field in the DSPIx_MCR is 0b01.
See Section 20.4.7, “Transfer Formats” for a description of the timing and transfer protocol.
See Section 20.3.2.10, “DSPI DSI Configuration Register (DSPIx_DSICR).”
The DSI frames can be from 4 to 16 bits long. With multiple transfer operation (MTO), the DSPI supports
serial chaining of DSPI modules within the MCU to create DSI frames consisting of concatenated bits
from multiple DSPIs. The DSPI also supports parallel chaining allowing several DSPIs and off-chip SPI
devices to share the same serial communications clock (SCK) and peripheral chip select (PCS) signals.
See Section 20.4.4.7, “Multiple Transfer Operation (MTO),” for details on the serial and parallel chaining
support.
20.4.4.1 DSI Master Mode
In DSI master mode the DSPI initiates and controls the DSI transfers. The DSI master has four different
conditions that can initiate a transfer:
• Continuous
• Change in data
• Trigger signal
• Trigger signal combined with a change in data
The four transfer initiation conditions are described in Section 20.4.4.5, “DSI Transfer Initiation Control.”
Transfer attributes are set during initialization. The DSICTAS field in the DSPIx_DSICR determines
which of the DSPIx_CTARs controls the transfer attributes.
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