NXP Semiconductors MPC5566 - Register Description

Enhanced Modular Input/Output Subsystem (eMIOS)
MPC5566 Microcontroller Reference Manual, Rev. 2
17-8 Freescale Semiconductor
17.3.1 Register Description
All registers are 32-bit wide. This section describes the eMIOS with 24 unified channels supporting 24-bit
wide data.
17.3.1.1 eMIOS Module Configuration Register (EMIOS_MCR)
EMIOS_MCR contains global control bits for the eMIOS module.
The following table describes the fields in the eMIOS module configuration register:
Address: Base + 0x0000 Access: R/W
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
0 MDIS FRZ GTBE ETB GPREN
000000
SRV
W
Reset00000 0 0000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
GPRE
00000000
W
Reset00000 0 0000000000
Figure 17-2. eMIOS Module Configuration Register (EMIOS_MCR)
Table 17-6. EMIOS_MCR Field Descriptions
Field Description
0 Reserved. This bit is readable and writable, but has no effect.
1
MDIS
Module disable. Puts the eMIOS in low power mode. The MDIS bit is used to stop the clock of the module,
except the access to registers EMIOS_MCR and EMIOS_OUDR.
0 Clock is running
1 Enter low power mode
2
FRZ
Freeze. Enables the eMIOS to freeze the registers in the unified channels when debug mode is requested at
the MCU level. Set the FREN bit in each unified channel to enter freeze mode. While in freeze mode, the
eMIOS continues to operate to allow the MCU access to the unified channels registers. The unified channel
remains frozen until:
• FRZ bit is cleared to zero; or,
• MCU exits debug mode; or,
• Unified channel FREN bit is cleared
0 Allows unified channels to continue to operate when device enters debug mode and the
EMIOS_CCRn[FREN] bit is set
1 Stops unified channels operation when in debug mode and the EMIOS_CCRn[FREN] bit is set
3
GTBE
1
Global time base enable. Used to export a global time base enable from the module and provide a method to
start time bases of several modules simultaneously.
0 Global time base enable out signal negated
1 Global time base enable out signal asserted
Note: The global time base enable input signal controls the internal counters. When asserted, internal
counters are enabled. When negated, internal counters disabled.