Enhanced Time Processing Unit (eTPU)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 18-15
18.4.2 eTPU Register Addresses
Table 18-5 shows the eTPU registers and their locations, without examples or explanation of how the fields
are used. For a complete description of these registers, refer to the Enhanced Time Processing Unit (eTPU)
Reference Manual. The features are explained in detail there.
Base + (0x0001_0000–0x0001_4FFF) Shared code memory (20 KB)
Base + (0x0001_5000–0x0001_FFFF) Not writable. Reads the return value of ETPU_SCMOFFDATAR register.
1
Parameter Sign Extension access area. Refer to the eTPU Reference Manual.
Table 18-5. Detailed Memory Map
Address Register Name Register Description Bits
Base = 0xC3FC_0000 ETPU_MCR eTPU module configuration register 32
Base + 0x0000_0004
ETPU_CDCR
eTPU coherent dual-parameter controller
register
32
Base + 0x0000_0008 — Reserved —
Base + 0x0000_000C ETPU_MISCCMPR eTPU MISC compare register 32
Base + 0x0000_0010 ETPU_SCMOFFDATAR eTPU SCM off-range data register 32
Base + 0x0000_0014 ETPU_ECR_A eTPU A engine configuration register 32
Base + 0x0000_0018 ETPU_ECR_B
1
eTPU B engine configuration register 32
Base + 0x0000_001C — Reserved —
Base + 0x0000_0020 ETPU_TBCR_A eTPU A time base configuration register 32
Base + 0x0000_0024 ETPU_TB1R_A eTPU A time base 1 32
Base + 0x0000_0028 ETPU_TB2R_A eTPU A time base 2 32
Base + 0x0000_002C
ETPU_REDCR_A
eTPU A STAC bus interface configuration
register
32
Base + (0x0000_0030–0x0000_003F) — Reserved —
Base + 0x0000_0040 ETPU_TBCR_B
1
eTPU B time base configuration register 32
Base + 0x0000_0044 ETPU_TB1R_B
1
eTPU B time base 1 32
Base + 0x0000_0048 ETPU_TB2R_B
1
eTPU B time base 2 32
Base + 0x0000_004C
ETPU_REDCR_B
1
eTPU B STAC bus interface configuration
register
32
Base + (0x0000_0050–0x0000_01FF) — Reserved —
Base + 0x0000_0200 ETPU_CISR_A eTPU A channel interrupt status register 32
Base + 0x0000_0204 ETPU_CISR_B
1
eTPU B channel interrupt status register 32
Base + 0x0000_0208 — Reserved —
Table 18-4. eTPU High-Level Memory Map (continued)
Address Register Description
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