System Integration Unit (SIU)
MPC5566 Microcontroller Reference Manual, Rev. 2
6-38 Freescale Semiconductor
Refer to Table 6-19 for bit field definitions. Table 6-36 lists the PA fields for
DATA[31]_FEC_RXD[3]_GPIO[59].
6.3.1.36 Pad Configuration Registers 60–61 (SIU_PCR60–SIU_PCR61)
The SIU_PCR60–SIU_PCR61 registers control the function, direction, and electrical attributes of
TSIZ[0:1]_GPIO[60:61].
Figure 6-37. TSIZ[0:1]_GPIO[60:61] Pad Configuration Register (SIU_PCR60–SIU_PCR61)
Refer to Table 6-19 for bit field definitions. Table 6-46 lists the PA fields for TSIZ[0:1]_GPIO[60:61].
Table 6-36. PCR59 PA Field Descriptions
PA Field Pin Function
0b00 GPIO[59]
0b01 DATA[31]
0b10 FEC_RXD[3]
0b11 DATA[31]
Address: Base + (0x00B8–0x00BA) Access: R/W
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0 0
PA OBE
1
1
When configured as TSIZ[0:1], the OBE bit has no effect. When configured as GPDO, set the OBE bit to 1.
IBE
2
2
When the pad is configured as an output, set the IBE bit to 1 to show the pin state in the GPDI register.
Clear the IBE bit to 0 to reduce power consumption. When configured as GPDI, set the IBE bit to 1.
DSC ODE
3
3
When configured as TSIZ[0:1], clear the ODE bit to 0.
HYS
4
4
If external master operation is enabled, clear the HYS bit to 0.
0 0
WPE
5
5
Refer to the EBI section for weak pullup settings when configured as TSIZ[0:1].
WPS
5
W
RESET: 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1
Table 6-37. PCR60–PCR61 PA Field Definition
PA Field Pin Function
0b0 GPIO[60:61]
0b1 TSIZ[0:1]
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