Enhanced Queued Analog-to-Digital Converter (eQADC)
MPC5566 Microcontroller Reference Manual, Rev. 2
19-96 Freescale Semiconductor
19.4.6.2 External Multiplexing
The eQADC can use from one to four external multiplexers to expand the number of analog signals that
may be converted. Using this configuration, up to 25 additional channels can be created.
• The first external multiplexer requires one common analog pin and three address pins, so although
eight additional ADC channels are created, four existing channels are lost, so there is a net addition
of four channels.
• For subsequent external multiplexers, only one additional internal channel is lost so there is a net
addition of seven channels.
The externally multiplexed channels are automatically selected by the CHANNEL_NUMBER field of a
command message, in the same way done with internally multiplexed channels. The software selects the
external multiplexed mode by setting the ADC0/1_EMUX bit in either ADC0_CR or ADC1_CR
depending on which ADC performs the conversion. Figure 19-52 shows the channel number assignments
for the multiplexed mode. Only one ADC can have its ADC0/1_EMUX bit asserted at a time.
Table 19-52. Multiplexed Channel Assignments
1
1
The two on-chip ADCs can access the same analog input pins but simultaneous conversions are not allowed. Also, when
one ADC is performing a differential conversion on a pair of pins, the other ADC must not access either of these two pins
as single-ended channels.
Input Pins
Channel Number in
CHANNEL_NUMBER Field
Analog
Pin Name
Other Functions Conversion Type Binary Decimal
AN[0]–AN[7] Single-ended 0000_0000–0000_0111 0–7
Used for digital address lines of the external mux 0000_1000–0000_1011 8–11
AN[12]–AN[39] Single-ended 0000_1100–0010_0111 12–39
V
RH
Single-ended 0010_1000 40
V
RL
Single-ended 0010_1001 41
(V
RH
– V
RL
) ÷ 2 Single-ended 0010_1010 42
75% x (V
RH
– V
RL
) Single-ended 0010_1011 43
25% x (V
RH
– V
RL
) Single-ended 0010_1100 44
Reserved 0010_1101–0011_1111 45–63
ANW
ANX
ANY
ANZ
—
—
—
—
Single-ended
Single-ended
Single-ended
Single-ended
0100_0xxx
0100_1xxx
0101_0xxx
0101_1xxx
64–71
72–79
80–87
88–95
DAN0+ and DAN0-
DAN1+ and DAN1-
DAN2+ and DAN2-
DAN3+ and DAN3-
Differential
Differential
Differential
Differential
0110_0000
0110_0001
0110_0010
0110_0011
96
97
98
99
Reserved 0011_0100–1111_1111 100–255
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