NXP Semiconductors MPC5566 - Flash ECC Attributes Register (ECSM_FEAT); Flash ECC Master Number Register (ECSM_FEMR)

Error Correction Status Module (ECSM)
MPC5566 Microcontroller Reference Manual, Rev. 2
8-8 Freescale Semiconductor
8.2.1.7 Flash ECC Master Number Register (ECSM_FEMR)
The FEMR is an 8-bit register for capturing the XBAR bus master number of the last, correctly-enabled
ECC event in the flash memory. Depending on the state of the ECSM_ECR, an ECC event in the flash
loads the address, attributes and data of the access into the ECSM_FEAR, ECSM_FEMR, ECSM_FEAT
and ECSM_FEDR registers, and asserts the FNCE flag in the ECSM_ESR.
8.2.1.8 Flash ECC Attributes Register (ECSM_FEAT)
The ECSM_FEAT is an 8-bit register for capturing the XBAR bus master attributes of the last,
correctly-enabled ECC event in the flash memory. Depending on the state of the ECSM_ECR register, an
ECC event in the flash loads the address, attributes and data of the access into the ECSM_FEAR,
ECSM_FEMR, ECSM_FEAT, and ECSM_FEDR registers, and asserts the FNCE flag in ECSM_ESR.
Table 8-5. ECSM_FEAR Field Descriptions
Field Description
0–31
FEAR
[0:31]
Flash ECC address. Contains the faulting access address of the last, correctly-enabled flash ECC event.
ECSM Base + 0x0056 Access: Read
01234567
R0000 FEMR
W
Reset
1
0000UUUU
1
“U” signifies a bit that is uninitialized.
Figure 8-5. Flash ECC Master Number Register (ECSM_FEMR)
Table 8-6. ECSM_FEMR Field Descriptions
Field Description
0–3 Reserved.
4–7
FEMR
[0:3]
Flash ECC master number. Contains the XBAR bus master number of the faulting access of the last,
correctly-enabled flash ECC event. The reset value of this field is undefined.