NXP Semiconductors MPC5566 - Physical Address Low Register (PALR)

Fast Ethernet Controller (FEC)
MPC5566 Microcontroller Reference Manual, Rev. 2
15-22 Freescale Semiconductor
15.3.4.2.11 Physical Address Low Register (PALR)
The PALR is written by the application. This register contains the lower 32 bits (bytes 0,1,2,3) of the 48-bit
MAC address used in the address recognition process to compare with the DA (destination address) field
of receive frames with an individual DA. In addition, this register is used in bytes 0 through 3 of the 6-byte
source address field when transmitting PAUSE frames. This register is not reset and must be initialized by
the application.
Table 15-15 describes the field and function in the physical address low register (PALR):
Address: Base + 0x00E4 Access: User R/W
0 123456789101112131415
R
PADDR1
W
Reset U
1
UUUUUUUUUUU U U U U
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
PADDR1
W
ResetUUUUUUUUUUUU U U U U
1
“U” signifies a bit that is uninitialized.
Figure 15-13. Physical Address Low Register (PALR)
Table 15-15. PALR Field Descriptions
Field Description
0–31
PADDR1
Bytes 0 (bits 0:7), 1 (bits 8:15), 2 (bits 16:23) and 3 (bits 24:31) of the 6-byte individual address to
be used for exact match, and the Source Address field in PAUSE frames.