NXP Semiconductors MPC5566 - Flash ECC Data High Register (ECSM_FEDRH)

Error Correction Status Module (ECSM)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 8-9
8.2.1.9 Flash ECC Data High Register (ECSM_FEDRH)
The ECSM_FEDRH and ECSM_FEDRL are 32-bit registers for capturing the data of the last,
correctly-enabled ECC event in flash memory. Depending on the state of the ECSM_ECR, an ECC event
in the flash loads the address, attributes and data of the access into the ECSM_FEAR, ECSM_FEMR,
ECSM_FEAT and ECSM_FEDR registers, and asserts the FNCE flag in ECSM_ESR.
Base + 0x0057 Access: Read
01234567
R WRITE SIZE PROT0 PROT1 PROT2 PROT3
W
Reset
1
UUUUUUUU
1
“U” signifies a bit that is uninitialized.
Figure 8-6. Flash ECC Attributes Register (ECSM_FEAT)
Table 8-7. ECSM_FEAT Field Descriptions
Field Description
0
WRITE
Write. The reset value of this field is undefined.
0 System bus read access
1 System bus write access
1–3
SIZE
[0:2]
Size. The reset value of this field is undefined.
000 8-bit System bus access
001 16-bit System bus access
010 32-bit System bus access
011 64-bit System bus access
1xx Reserved
4
PROT0
Protection: cache. The reset value of this field is undefined.
0 Non-cacheable
1 Cacheable
5
PROT1
Protection: buffer. The reset value of this field is undefined.
0 Non-bufferable
1Bufferable
6
PROT2
Protection: mode. The reset value of this field is undefined.
0User mode
1 Supervisor mode
7
PROT3
Protection: type. The reset value of this field is undefined.
0 I-Fetch
1 Data