NXP Semiconductors MPC5566 - EBI Option Registers 0-3 (Ebi_Orn) and EBI Calibration Option Registers

External Bus Interface (EBI)
MPC5566 Microcontroller Reference Manual, Rev. 2
12-20 Freescale Semiconductor
12.3.1.7 EBI Option Registers 0–3 (EBI_ORn) and EBI Calibration Option
Registers 0–3 (EBI_CAL_ORn)
The EBI_ORn registers are used to define the address mask and other attributes for the corresponding chip
select. The EBI_CAL_ORn registers are used to define the address mask and other attributes for the
corresponding calibration chip select.
The following table describes the fields in the EBI calibration option registers:
Address: Base + 0x0014 (EBI_OR0)
Base + 0x001C (EBI_OR1)
Base + 0x0024 (EBI_OR2)
Base + 0x002C (EBI_OR3)
Base + 0x0044 (EBI_CAL_OR0)
Base + 0x004C (EBI_CAL_OR1)
Base + 0x0054 (EBI_CAL_OR2)
Base + 0x005C (EBI_CAL_OR3)
Access: R/W
0123456789101112131415
R111
AM
W
Reset1110000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
AM
0000000
SCY
0
BSCY
0
W
Reset0000000000000000
Figure 12-6. EBI Option Registers 0–3 (EBI_ORn) and EBI Calibration Option Registers
Table 12-11. EBI_ORn and EBI_CAL_ORn Field Descriptions
Field Description
0–16
AM
[0:16]
Address mask. Allows masking of any corresponding bits in the associated base register. Masking the address
independently allows external devices of different size address ranges to be used. Any clear bit masks the
corresponding address bit. Any set bit causes the corresponding address bit to be used in comparison with the
address pins. Address mask bits can be set or cleared in any order in the field, allowing a resource to reside in more
than one area of the address map. This field can be read or written at any time.
Note: The upper 3 bits of the address mask (AM) field, EBI_ORx[0:2], and EBI_CAL_ORn[0:2], are tied to a fixed
value of 111. These bits reset to their fixed value.
17–23 Reserved.
24–27
SCY
[0:3]
Cycle length in clocks. Represents the number of wait states (external bus cycles) inserted after the address phase
in the single cycle case, or in the first beat of a burst, when the memory controller handles the external memory
access. Values range from 0 to 15. This is the main parameter for determining the length of the cycle.
• The total cycle length for the first beat (including the TS
cycle):
See Section 12.5.3.1, “Example Wait State Calculation”.
28 Reserved.
(2 + SCY) external clock cycles