Enhanced Modular Input/Output Subsystem (eMIOS)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 17-27
17.4.4.1 Programmable Input Filter (PIF)
The PIF ensures that only valid input pin transitions are received by the unified channel edge detector.
A block diagram of the PIF is shown in Figure 17-14.
The PIF is a 5-bit programmable up counter that is incremented by the selected clock source, according to
bits IF[0:3] in EMIOS_CCRn. The clock source is selected by the EMIOS_CCRn[FCK] bit.
Figure 17-14. Programmable Input Filter Submodule Diagram
The input signal is synchronized by the system clock. When a state change occurs in this signal, the 5-bit
counter starts counting up. As long as the new state is stable on the pin, the counter continues incrementing.
If a counter overflows occurs, the new pin value is validated. In this case, it is transmitted as a pulse edge
to the edge detector. If the opposite edge appears on the pin before validation (overflow), the counter is
reset. At the next synchronized pin transition, the counter starts counting again. Any pulse that is shorter
than a full range of the masked counter is regarded as a glitch, and it is not passed on to the edge detector.
A timing diagram of the input filter is shown in Figure 17-15.
Figure 17-15. Programmable Input Filter Example
Synchronizer
IF3
CLK
IF2 IF1 IF0
5-bit up counter
FCK
Prescaled clock
EMIOSn
Clock
System clock
Filter out
Selected clock
5-bit counter
IF = 0b0011
Filter out
EMIOSn
Time
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